Senior SoC Physical Layout & Full-Chip Integration Engineer
Core
Lead full-chip floorplanning, physical integration, and tapeout for advanced-node silicon development vehicles.
Role type
Senior IC physical design engineer (full-chip integration)
Builds
Custom layout methodologies and full-chip silicon platforms for advanced process nodes
Domain
Semiconductor manufacturing / Advanced-node physical design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: physical/clinical work -> physical/clinical work is wrong, correct is: physical/clinical work is not applicable. The deliverable is physical silicon chips/layouts. The schema options are fixed. Let's re-evaluate the schema options: 'production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work'. None fit perfectly, but 'physical/clinical work' is the closest semantic match for hardware manufacturing, or 'infrastructure' for the flow. However, the instruction says 'one of'. I will select 'physical/clinical work' as it is the only one related to physical hardware creation, though 'infrastructure' might be a stretch. Actually, looking at the list again, none are perfect. But 'physical/clinical work' is the only one involving physical objects. Let's assume the schema is rigid. I will use 'physical/clinical work' as the closest fit for hardware layout, or perhaps the prompt implies a broader definition. Wait, the prompt says 'one of: ...'. I must choose one. 'physical/clinical work' is the only one that isn't software/data. I will use it.
Required skills
Custom/analog/mixed-signal layout design, Front-end (FEOL) layout design rules, Physical verification (LVS, DRC, DFM), Tcl/Python/SKILL scripting, Floorplanning, RDL/bump planning, PowerVia implementation
Preferred skills
PDK collaboration, Tapeout schedule management, Custom layout environments (Cadence Virtuoso), NDM flows
Technologies
Calibre, ICV, Cadence Virtuoso, Tcl, Python, SKILL
Responsibilities
Lead full-chip floorplanning and physical integration, Develop custom layout methodologies, Drive physical verification closure, Analyze advanced-node design rules, Develop automation solutions, Coordinate cross-functional tapeout activities
Seniority
Senior, hands-on IC