Memory Layout Manager
Core
Lead a team of layout engineers to deliver best-in-class SRAM, RF, ROM, and CAM memory compiler designs on Intel's FinFET and GAA technologies.
Role type
Senior IC layout design engineering manager (memory compilers)
Builds
High-density, performance-optimized memory compilers for Intel Foundry
Domain
Semiconductor manufacturing / VLSI / Memory technologies
Deliverable
production ML models | product features
Required skills
Memory compiler layout design, floorplanning, placement and routing, DRC/LVS/Yield/DFM analysis, EM/IR noise reliability, team leadership, project management, EDA flow automation (SKILL/Python/Tcl), analog/digital/memory/standard cell methodologies
Preferred skills
AI/ML integration for design automation, strategic decision-making, innovation culture building
Technologies
Cadence Virtuoso, Siemens Calibre, Synopsys IC Validator, FinFET, GAA
Responsibilities
Lead and mentor layout engineers; oversee design and verification of memory compiler layouts; provide technical guidance on layout methodologies and flows; enable teams using AI-driven EDA tools; manage resources to meet performance targets
Seniority
Senior, hands-on IC with management responsibilities
