Senior DFT Logic Design Engineer
Core
Provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodology and flows for ASIC and SOC designs.
Role type
Senior IC DFT Logic Design Engineer
Builds
ASIC DFT/DFM and ATPG validation flows and documentation for block and SOC levels
Domain
Semiconductor foundry services, advanced CMOS processes, DFT/DFM, ATPG
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG), ATPG validation, DFT timing signoff, Python/Perl/Tcl/shell scripting, PDK knowledge, EDA tool suites
Preferred skills
Design implementation methodology (LVS, DRC, DFX/DFM), RTL and Hard IP design collaboration, physical design collaboration, technical direction to engineering teams, semiconductor foundry experience
Technologies
Python, Perl, Tcl, shell scripting, EDA tool suites, PDKs
Responsibilities
Collaborate with internal teams and external stakeholders on issue resolution; Create content, application notes, and deliver technical training; Drive quality of ASIC DFT/DFM and ATPG validation methodology and documentation; Support tool/flow/methodology for customer tape-outs
Seniority
Senior, hands-on IC