System Technology Research Engineer - (PhD Intern)
Core
Develop System Technology Co-optimisation (STCO) methodologies and evaluate 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding for memory and logic stacking.
Role type
PhD Research Engineer Intern (Semiconductor System Technology)
Builds
Intel's semiconductor processing and packaging roadmap
Domain
Semiconductor manufacturing, 3D/2.5D packaging, System Architecture
Deliverable
production ML models | product features | research
Required skills
System architecture modelling, digital circuit analysis and design, VLSI physical layout, electronic design automation, multi-physics modeling, IC design tools (Cadence Virtuoso, Synopsis Fusion Compiler)
Preferred skills
DRAM/SRAM circuit design, integrated circuits manufacturing flow, 2.5D/3D packaging technologies, 3DIC design and simulation, Python programming
Technologies
Cadence Virtuoso, Synopsis Fusion Compiler
Responsibilities
Develop and enhance STCO methodologies, Perform system-level evaluations of novel devices and integration schemes, Collaborate with diverse teams to drive innovation
Seniority
Intern (PhD candidate)
