CPU Floorplan Lead
Core
Defines physical dimensions of CPU IP, optimizes die size and technology selection, and integrates dies in a package for tapeout.
Role type
Senior IC physical design floorplan lead
Builds
CPU IP blocks and integrated packages
Domain
Semiconductor / VLSI / ASIC
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Floorplanning, pin placement, die size estimation, hierarchical design, timing and physical convergence, clock and power distribution, global signal planning, I-O planning, hard IP integration, DFT, mixed signal block integration, advanced package technologies, Design for Yield and Manufacturability
Preferred skills
Master's in Electrical-Electronics Engineering with VLSI-microelectronics specialization
Technologies
ICC2 DP, Cadence Encounter
Responsibilities
Optimize placement of IPs for latency and die area/aspect ratio; create physical database for IP; collaborate with architects, clock design, logic design, and power delivery teams; evaluate floorplan tools, methods, and flows; solve design issues at partition/cluster and full chip levels.
Seniority
Senior, hands-on IC