Silicon Packaging Design Engineer
Core
Drive end-to-end development of advanced substrate designs from concept through tape-out, ensuring optimal performance, cost efficiency, and manufactability for high-performance applications.
Role type
Silicon Packaging Design Engineer
Builds
Advanced substrate designs and package layouts
Domain
Semiconductor manufacturing / Silicon packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (substrate designs)
Required skills
microelectronic package physical layout design, PCB physical layout design, package design tools (Siemens Xpedition, Cadence Allegro, AutoCAD, SolidWorks), substrate design floor planning, DRC analysis, cross-functional collaboration
Preferred skills
microelectronic package substrate design, package I/O routing, electrical modeling and simulation (PowerDC, HyperLynx, Q3D, HFSS), package design automation (PLA, FIELD), scripting (Python, VB, C)
Technologies
Siemens Xpedition, Cadence Allegro, AutoCAD, SolidWorks, PowerDC, HyperLynx, Q3D, HFSS, PLA, FIELD
Responsibilities
Drive physical layout and routing of package designs, perform substrate fit and routing studies, define and implement substrate design rules, analyze data and resolve DRCs, optimize designs for manufacturability, collaborate on pinout and silicon-package-board interactions
Seniority
Entry-level to Mid-level (1+ years or Master's with 6 months)
