Circuit Design Intern, Master's or PhD (Summer 2027)
Core
Perform block-level physical design (place-and-route) and RTL simulation/verification for standard-cell and memory IP cores to optimize power, performance, and area for Edge AI and automotive applications.
Role type
Summer intern, IC circuit design engineer (physical design)
Builds
VLSI physical design flows and IP cores for Edge AI and automotive chips
Domain
Semiconductor manufacturing, VLSI, Edge AI, Automotive
Deliverable
production ML models
Required skills
Place-and-route, RTL simulation, standard-cell design, memory IP, Tcl/Perl scripting, CAD/EDA tools, VLSI circuit design
Preferred skills
UNIX, prior internship/co-op, leadership, AI tool usage, project management, planning & organization
Technologies
Place-and-route tools, RTL simulators, CAD/EDA tools, Tcl, Perl, UNIX
Responsibilities
Perform block-level place and route for complex cores using standard-cell and memory-library IP; Run RTL simulation and verification flows; Apply circuit-design techniques to optimize standard-cell logic; Develop and maintain Tcl and Perl scripts for automation; Optimize standard-cell and memory IP through block-level design studies; Use industry-standard CAD and EDA tools for VLSI implementation and debugging.
Seniority
Intern