Staff Engineer AI/ML
Core
Lead RTL development and micro-architecture design for AI-enabled RISC-V CPU cores, including vector extensions and matrix engines.
Role type
Senior IC CPU IP Design Engineer (AI/ML hardware)
Builds
RISC-V CPU cores with AI capabilities (vector/matrix engines) for physical AI applications
Domain
Semiconductor / Hardware Engineering / AI Hardware
Deliverable
production ML models | product features
Required skills
High-performance processor design, Vector/Matrix datapath design, Microprocessor architecture (fetch/decode, scheduling, out-of-order execution), System Verilog/Verilog/VHDL, RTL design for PPA/Timing, Simulation and waveform debugging, Logic design principles
Preferred skills
RISC-V/ARM/MIPS CPU design, Hardware multi-threading/virtualization/SIMD, Vector/matrix-enabled CPU experience, Low-power microarchitecture, SoC integration, Safety/Security microarchitecture, Python/Perl scripting
Technologies
RISC-V, System Verilog, Verilog, VHDL, Perl, Python
Responsibilities
Drive micro-architecture and design of critical CPU core blocks, Design RISC-V Vector CPU core and custom extensions, Design AI-enabled Matrix engine, Explore high-performance strategies with modeling team, Configure Design Features for PPA/Timing goals, Perform Functional verification support, Partner on physical design validation (timing, area, reliability, testability, power)
Seniority
Senior, hands-on IC
