Sr Staff Engineer
Core
Plans and executes advanced Design-for-Test (DFT) solutions for semiconductor chip development, focusing on building robust DFT flows for ATPG, MBIST, LBIST, and analog test.
Role type
Senior IC DFT Engineer
Builds
Robust DFT flows and reusable test IP for SoCs
Domain
Semiconductor manufacturing / Digital and Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ATPG, MBIST, LBIST, analog test development, scan insertion, DFT flow design, EDA tool usage, Python scripting, Perl scripting, TCL scripting
Preferred skills
Leadership of DFT teams, test time optimization, cross-functional collaboration
Technologies
Synopsys, Cadence, Mentor Graphics, Python, Perl, TCL
Responsibilities
Define and deploy DFT architecture for chips; Develop and validate test patterns; Collaborate cross-functionally to integrate DFT features; Analyze test performance data and apply lessons learned; Document DFT specifications and standards.
