Principal Engineer, Package Co-Design
Core
Lead die-package co-design strategy for custom silicon products (industrial, automotive, end-equipment), defining package architecture and driving system-level analysis.
Role type
Principal Engineer, Package Co-Design Leader
Builds
Custom silicon products with optimized package solutions for industrial, automotive, and other end-equipment markets.
Domain
Semiconductor manufacturing, packaging technologies, die-package co-design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (semiconductor packaging solutions)
Required skills
Die-package co-design strategy, package architecture definition, signal/power integrity analysis, thermal analysis, mechanical analysis, interface placement, IO ring development, floorplan optimization, validation and characterization, Design for Test (DFT), Design for Manufacturing (DFM), cross-disciplinary system leadership, vendor engagement, technical mentorship
Preferred skills
ASIC/SoC design experience (mixed-signal, high-speed, networking), foundry and OSAT partner engagement, industry standards contributions, patents or publications
Technologies
Flip-chip, WLCSP, FCBGA, wire-bond, 2.5D, 3D, interposers, chiplets, Cadence, Synopsys, Ansys, HFSS
Responsibilities
Lead die-package co-design strategy and drive overall packaging engagement; Define package architecture and drive early feasibility studies; Drive package co-design engineering work including interface placement and IO ring development; Perform system-level analysis (SI, PI, thermal, mechanical) and guide simulations; Define validation and characterization requirements for new productions; Provide technical guidance and mentorship to junior engineers; Lead customer and vendor engagement to drive technical alignment
Seniority
Principal, hands-on IC with leadership responsibilities
