3D Heterogeneous Integration Design Enablement Engineer (2026 New College Graduate)
Core
R&D design enablement engineer for 3D heterogeneous integration (3DHI) and advanced packaging, focusing on wafer-to-wafer bonding, die-to-wafer bonding, TSV/TOV, and interposer development.
Role type
Senior IC design enablement engineer (advanced packaging)
Builds
Design manuals (DM), process design kit (PDK) specifications, and test vehicle content for next-generation semiconductor packaging.
Domain
Semiconductor manufacturing / Advanced packaging
Required skills
3D heterogeneous integration design, wafer-to-wafer bonding, die-to-wafer bonding, TSV/TOV, interposer development, design rule creation, PDK development, test vehicle specification, mask review, OSAT collaboration
Preferred skills
EDA tools, semiconductor packaging process modules, project management, leadership experience
Technologies
TSV, TOV, PDK, EDA
Responsibilities
Publish Design Manual (DM) specifications based on failure modes; translate packaging requirements to device enablement specifications; develop expertise in drafting test vehicle content and tapeout processes; collaborate with vendors and OSATs on design and masks; facilitate advanced packaging design interactions between product lines/fab teams and customers.
Seniority
Junior, new college graduate (PhD or Master's required)
