Junior Digital Verification Engineer
Core
Execute full verification cycles for complex digital designs, implementing SystemVerilog Assertions and driving deep code coverage analysis.
Role type
Junior IC digital verification engineer
Builds
Functionally pristine memory blocks and finalized regression suites for Samsung's next-generation Flash memory products (SSD, eMMC/UFS)
Domain
Semiconductor hardware verification
Required skills
SystemVerilog, UVM, SystemVerilog Assertions (SVA), test execution, coverage closure, debug and trace analysis
Preferred skills
Python scripting, Linux/Unix environments, Cadence Xcelium, vManager, Indago
Responsibilities
Join the full verification cycle from planning to coverage closure; Implement SVA and drive deep code coverage analysis; Debug complex tests and trace analysis alongside design engineers; Collaborate closely with design and algorithm engineers (via careerplan.io/jobs/D4-005-E2-372-junior-digital-verification-engineer)
Seniority
Junior, hands-on IC
