Formal Verification Engineer
Core
Apply mathematical methods like model checking and equivalence checking to validate complex SoC designs without relying on simulation, detecting corner-case bugs early.
Role type
Senior IC formal verification engineer (SoC)
Builds
Validated SoC designs and verification environments for RPG products
Domain
Hardware design verification / SoC
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (verification environments)
Required skills
SoC verification, model checking, equivalence checking, property specification languages, assertion-based verification, hardware description languages, gate-level simulation debugging, APB/AXI protocols, PHY verification, high-speed block verification
Preferred skills
SME in formal verification methodologies, team leadership, cross-functional coordination, mentoring
Technologies
UVM, SystemVerilog, SVA, Questa, Verdi, Synopsys VCS, Cadence Xcelium
Responsibilities
Define test plans and develop test scripts for RPG product validation; Collaborate with architecture teams to define validation flows; Run and debug gate-level simulations; Lead development of formal verification methodologies; Mentor junior team members; Coordinate cross-functional efforts to align verification goals with project timelines
Seniority
Senior, hands-on IC with team leadership
