Principal DV Engineer
Core
Verify custom ASICs for satellite and wireless telephony systems to ensure connectivity from space.
Role type
Principal Digital Design Verification Engineer
Builds
Custom ASICs for IoT and satellite communications
Domain
Semiconductor / Space Communications
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog, SystemVerilog, UVM, C/C++, Perl, Python, bash scripting, RTL simulation debugging, gate-level simulation debugging, SDF timing analysis, test plan creation, code coverage closure
Preferred skills
VHDL
Technologies
Verilog, SystemVerilog, UVM, C, C++, Perl, Python, bash
Responsibilities
Build UVM verification environments from scratch, write and maintain comprehensive test suites, debug complex RTL and gate-level simulations, assess SDF timing violations, lead design verification efforts through chip tapeout
Seniority
Principal, hands-on IC
