Junior Design Verification Engineer, Amazon Leo
Core
Implementing verification environments to test RTL against reference models for digital communication-system chips in Low Earth Orbit satellites.
Role type
Junior IC design verification engineer (communication systems)
Builds
Digital communication-system chips for satellites and Amazon gateways
Domain
Aerospace/Telecommunications
Deliverable
production ML models | product features
Required skills
UVM, SystemVerilog, Verilog, MATLAB, C, regression testing, coverage analysis
Preferred skills
Formal verification, AI-assisted verification tools, SystemC model integration, Modem design verification
Technologies
AI, Embedded Matlab, SystemVerilog, Verilog, Hardware Support
Responsibilities
Implement verification environments to test RTL against reference models; Develop test plans, run regressions, and gather coverage data; Validate ASIC implementations in Verilog and SystemVerilog; Collaborate on system-level verification using UVM testbenches; Build automated regression environments.
Seniority
Junior, hands-on IC
