DFT Engineer
Core
Design and validate DFT architectures for ASIC/SoC designs to ensure high manufacturing test coverage and efficient silicon bring-up.
Role type
DFT Engineer
Builds
ASIC and SoC designs with robust testability for semiconductor manufacturing
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Automatic Test Pattern Generation (ATPG), RTL design and debugging, scan insertion and compression, fault modeling, DFT rule checking, EDA tools for DFT
Preferred skills
JTAG and boundary scan implementation, MBIST/LBIST techniques, scripting (Tcl/Perl/Python), low-power DFT, synthesis and timing analysis
Technologies
ATPG tools, EDA tools, Tcl, Perl, Python
Responsibilities
Develop and implement DFT architectures for complex ASIC and SoC designs; Perform scan insertion, scan chain stitching, and compression implementation; Generate and optimize test patterns using ATPG tools; Analyze stuck-at, transition, bridge, and path delay faults; Collaborate with RTL designers to integrate DFT features early; Review and debug RTL code to resolve DFT-related issues; Validate DFT implementation through simulation and silicon bring-up; Support post-silicon debug and failure analysis; Maintain DFT documentation and test plans.
Seniority
Mid-Senior, hands-on IC
