DFT Integration Lead
Core
Lead DFT design and integration for cutting-edge semiconductor SoCs, focusing on SCAN, ATPG, MBIST, and BSCAN structures to ensure testability and debug capabilities.
Role type
Senior IC DFT Integration Lead
Builds
Testable and debuggable System-on-Chip (SoC) designs for leading process technologies
Domain
Semiconductor / ASIC Design
Required skills
ASIC DFT design, DFT architecture, RTL development (Verilog/System Verilog), EDA tools (Tessent, Design Compiler, Spyglass), scripting (Perl, Python, TCL), static timing analysis, IP integration
Preferred skills
Low power concepts, post-silicon bring up, end-to-end DFT flow development
Technologies
Tessent, Design Compiler, Spyglass, Verilog, System Verilog, Perl, Python, TCL
Responsibilities
Align DFT requirements with architecture and IP teams, design correct-by-construction DFT structures, support DFT verification, accelerate functional defect identification, develop test patterns and flows
Seniority
Senior, hands-on IC
