Senior Analog layout Engineer
Core
Design high-performance analog and digital circuits (ADCs, DACs, PLLs, HBM, GDDR, DDR, LPDDR, References, Custom IOs, LDO, ESD) for advanced process nodes (7nm and below) integrated into AMD products.
Role type
Staff Analog Layout Design Engineer
Builds
High-performance analog/digital ICs for AMD products
Domain
Semiconductor / Analog IC Design
Required skills
Analog layout design for mixed analog/digital ICs, Floorplanning, Power grid planning, Signal flow planning, LVS/DRC/ERC/ANT/ESD/Latch-up/EMIR/Reliability verification, Signal and clock shielding, Process non-idealities mitigation (STI stress, well proximity, CMP effects), CMOS circuit theory, High-speed circuit design (GHz)
Preferred skills
Layout design and verification using Cadence Virtuoso and Mentor Calibre tools, Chip level integration knowledge
Technologies
Cadence Virtuoso, Mentor Calibre, 7nm CMOS process
Responsibilities
Perform layout design for mixed analog/digital ICs, Execute floorplanning and power grid planning, Conduct verification (LVS, DRC, ERC, etc.), Mitigate process non-idealities, Collaborate with various teams to articulate specs
Seniority
Staff, hands-on IC
