LEC/CLP Engineer
Core
Plan and execute Logic Equivalence Checking (LEC) and Clock Latency Planning (CLP) for IP Subsystems and signoff at the physical partition level.
Role type
Senior IC silicon design engineer (verification/physical design)
Builds
IP Subsystems and device partitions
Domain
Semiconductor / Digital IC Design
Required skills
LEC, CLP, Synopsys/Cadence toolsets, synthesis flows, Low Power (UPF), complex design debugging, scripting/automation
Preferred skills
LEC/CLP signoff ownership, CAD team collaboration, EDA vendor management
Technologies
Synopsys, Cadence, UPF
Responsibilities
Execute LEC and CLP for all physical partitions including waivers and reviews, collaborate with design/implementation teams, drive team planning and status reporting, debug and resolve LEC/CLP issues with CAD teams or EDA vendors
Seniority
Senior, hands-on IC
