Engineer
Core
Synthesize, floorplan, place and route, and optimize CPU cores, system interconnect, and ARM designs to ensure RTL-GDS closure and timing/power/area quality.
Role type
Senior IC physical design engineer (ASIC implementation)
Builds
Custom SoC and CPU chip designs for Arm and partners
Domain
Semiconductor / ASIC Physical Design
Required skills
ASIC implementation, Physical design, STA, Timing closure, DFT, Floor planning, Place and Route, CTS, Power analysis, DFM, Physical verification, Tcl, Perl, Python, Make
Preferred skills
Arm based SoCs, Low power design techniques, Verilog RTL design, ATPG tools (via careerplan.io/jobs/100112429248-engineer-at-arm)
Technologies
Calibre, Primetime, Tcl, Perl, Python, Make, Verilog
Responsibilities
Synthesis, DFT, Floorplan, Place and Route, CTS and Optimization of CPU cores, system interconnect and other ARM Designs; Analyze design timing, area and power; Perform Layout edit for Physical Verification closure; Perform Timing ECO for design closure; Convert R&D concepts into real implementation solutions.
Seniority
Mid-level, hands-on IC
