Sr. Director of Packaging Engineering
Core
Lead strategy, development, and execution of advanced IC packaging technologies for AMD's silicon product portfolio, guiding packages from concept through high-volume manufacturing.
Role type
Senior Director of Packaging Engineering (Strategic & Technical Leadership)
Builds
Advanced IC packages (WLCSP, flip-chip, SiP, 2.5D/3D, chiplet architectures) for high-performance silicon products.
Domain
Semiconductor / IC Packaging / Heterogeneous Integration
Required skills
IC packaging strategy, global team leadership, end-to-end NPI/HVM management, signal integrity (SI/PI) co-design, thermal/mechanical co-design, OSAT/supplier partnership management, heterogeneous integration, budget and program planning
Preferred skills
Advanced packaging technologies (WLCSP, flip-chip, SiP, 2.5D/3D, chiplets), high-speed interface optimization, power delivery network (PDN) design, thermal simulation (FEA/CFD), warpage/stress management
Technologies
WLCSP, flip-chip, chip-on-chip, multi-chip module, system-in-package (SiP), 2.5D/3D integration, chiplet interconnect, SerDes, FEA, CFD
Responsibilities
Champion design-for-manufacturability and cost optimization; mentor and grow global engineering teams; own packaging development from concept to HVM; direct SI/PI and thermal/mechanical design strategies; manage OSAT and supply chain partnerships; drive technology standardization; represent packaging strategy to executives and customers; establish engineering budgets and schedules
Seniority
Senior Director, Strategic & Technical Leadership
