Senior Full chip EM/IR analysis Engineer
Core
Build, execute, and sign off on Power and Electromigration/IR (EMIR) closure for IP and full-chip System on Chip (SoC) designs.
Role type
Senior IC Physical Design/EMIR Analysis Engineer
Builds
Full-chip SoC designs and IP blocks
Domain
Semiconductor / VLSI Physical Design
Required skills
EMIR signoff strategy definition, IR drop and electromigration analysis, floorplan and clocking review, bump allocation coordination, EMIR flow ownership, technical leadership, scripting (Shell, Python, Perl, TCL, UNIX), physical design flows (Synthesis, ICC2, Fusion Compiler), signoff tools (Redhawk_Sc, Voltas, PT-PX, Primetime), DFx and scan architecture knowledge
Preferred skills
Mentorship of design engineers, cross-timezone collaboration, AI technology application in problem solving
Technologies
Redhawk_Sc, Voltas, PT-PX, Primetime, ICC2, Fusion Compiler, Shell, Python, Perl, TCL, UNIX
Responsibilities
Define EMIR signoff strategy including IR drop and electromigration analysis, Review floorplan, clocking, and bus structures for IR hotspots, Coordinate bump allocation and power rail alignment with integration teams, Work with block owners and PD teams to execute EMIR runs, Conduct EMIR run reviews and debug sessions, Maintain and improve EMIR flow
Seniority
Senior, hands-on IC with technical leadership
