Lead Full Chip Floorplan Design Engineer
Core
Lead Full Chip Floorplan Design Engineer responsible for developing and optimizing full-chip floorplans, partitioning strategies, power planning, and physical architecture for complex SoCs and ASICs to achieve aggressive PPA targets.
Role type
Senior IC physical design engineer (full-chip floorplanning)
Builds
Complex SoCs and ASICs for SSD Custom Silicon
Domain
Semiconductor / ASIC Physical Design
Required skills
Full-chip floorplanning, macro placement, power grid architecture, timing-driven floorplanning, congestion analysis, thermal-aware planning, IO and package planning, clock distribution planning, EMIR-aware planning, automation scripting
Preferred skills
12+ years ASIC/SoC Physical Design experience, expertise in full-chip floorplanning
Technologies
SoC, ASIC, PPA, EMIR, PCIe, SerDes, DDR, Ethernet, C2C
Responsibilities
Develop top-level SoC floorplan architecture including die size and partitioning strategy; Perform macro placement and optimization for timing, congestion, power, and thermal; Define power domain strategy, voltage islands, and power grid architecture; Optimize high-speed interface placement and drive chip-package co-design; Develop timing-driven floorplans and clock distribution architecture; Identify congestion hotspots and implement mitigation strategies; Develop scripts and automation for floorplan generation and analysis.
Seniority
Senior, hands-on IC
