Lead Full-chip STA and timing signoff Engineer
Core
Lead full-chip timing closure and signoff for complex SoC/ASIC designs from synthesis through tapeout.
Role type
Senior IC full-chip STA and timing signoff engineer
Builds
Complex SoC/ASIC designs in advanced technology nodes
Domain
Semiconductor / ASIC/SoC Physical Design
Required skills
Full-chip Static Timing Analysis (STA), Timing Signoff, MMMC flows, SDC constraint development, SI/crosstalk analysis, ECO closure, PVT corner analysis, Clocking architecture, CDC analysis, Variation effects (OCV/AOCV/POCV), Tapeout readiness
Preferred skills
Advanced technology node experience (7nm, 5nm, 3nm), Synthesis and place-and-route flows, Hierarchical timing integration, Timing budgeting, Mentorship
Technologies
Synopsys Design Compiler, PrimeTime, Innovus, ICC2, Calibre, Mentor Graphics, Cadence
Responsibilities
Lead full-chip timing closure across all modes and corners; Drive timing signoff from synthesis to tapeout; Develop and maintain timing constraints (SDC); Perform and review STA for setup, hold, recovery, removal, and async paths; Resolve timing violations related to datapath, clock path, and crosstalk; Lead timing ECO strategies; Collaborate with RTL and physical design teams on floorplanning and optimization; Mentor junior engineers and define best practices.
Seniority
Senior, hands-on IC with leadership responsibilities
