SoC Lead Engineer – LEC & Low Power Signoff
Core
Lead Low Power Static Verification and Logical Equivalence Check (LEC) signoff for System-on-Chip (SoC) designs from RTL to physical netlist.
Role type
Senior IC SoC Verification Lead (LEC & Low Power)
Builds
Full-chip and block-level SoC designs for AMD processors
Domain
Semiconductor / SoC Design / Verification
Required skills
Logical Equivalence Check (LEC), Low Power Static Verification, Verilog, VHDL, UPF methodology, EDA tool scripting (Tcl, Perl, Python), team leadership
Preferred skills
Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence CLP, Design Compiler, Fusion Compiler, PrimeTime, IC Compiler II, SoC tapeout experience
Technologies
Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence CLP, Design Compiler, Fusion Compiler, PrimeTime, IC Compiler II, UPF, Verilog, VHDL, Tcl, Perl, Python
Responsibilities
Lead and own the full LEC signoff chain from RTL to physical netlist; Drive full-chip top-level and tile-level low power static checks; Debug and resolve logical equivalence and low power static check issues; Lead a small team, owning task delivery and milestone tracking; Guide team members on LEC strategy and track design changes
Seniority
Senior, hands-on IC with leadership
