Senior STA Design Engineer
Core
Develop complex multi-mode/multi-corner timing constraints for RTL and signoff, drive timing closure for sub-chips/subsystems or full chips, and ensure quality handoff for Static Timing Analysis (STA) checks.
Role type
Senior IC STA Design Engineer
Builds
High-frequency processor subsystems and full chips
Domain
Semiconductor / Digital IC Design
Required skills
Static Timing Analysis (STA), SDC constraints, Tcl scripting, EDA tool proficiency, timing closure, OCV/AOCV/POCV analysis, DFT timing modes
Preferred skills
High-frequency block timing (>GHz), hierarchical/flat flow experience, Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker, DMSA
Technologies
Synopsys Design Compiler, Synopsys Primetime, Spyglass, Fishtail, Tweaker, DMSA, Tcl, Linux
Responsibilities
Develop complex multi-mode/multi-corner timing constraints compatible for RTL and signoff; Ensure constraints quality (SDC) using industry tools like Fishtail and GCA; Drive pre-route timing checks and QoR clean up to eliminate SDC issues; Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip; Ensuring Subsystem/full chip level Interface timing closure along DRV closure; Generating timing ECO using tools DMSA/Tweaker.
Seniority
Senior, hands-on IC
