PD CAD Engineer
Core
Develop and automate Place and Route (PnR) flows and methodologies for next-generation GPU and CPU designs at advanced technology nodes (3nm, 2nm).
Role type
Senior IC physical design automation engineer
Builds
Next-gen GPU and CPU silicon products
Domain
Semiconductor / Physical Design Automation
Required skills
Place and Route (PnR) flow development, Synthesis, Static Timing Analysis (STA), Physical Verification, Low-power flow (UPF, power-gating), Scripting (Python, TCL), EDA tool expertise (Cadence Innovus), Debugging
Preferred skills
Multi-voltage design, AI/ML concepts, Cross-site collaboration, Advanced node methodology (3nm/2nm)
Technologies
Cadence Innovus, Python, TCL, UPF, STA, GDSII
Responsibilities
Develop PnR methodologies for advanced nodes, Automate implementation flow utilities, Collaborate with synthesis and signoff teams, Support global design teams through chip finish flows, Drive PPA convergence for SOCs
Seniority
Senior, hands-on IC
