Sr DFT ATPG Lead
Core
Implement and verify DFT architecture and features for cutting-edge processor designs, ensuring first-pass silicon success.
Role type
Senior IC DFT ATPG Engineer
Builds
Front-end silicon designs for Radeon Technologies Group
Domain
Semiconductor / Digital IC Design
Required skills
DFT architecture implementation, Scan insertion, ATPG pattern generation, Gate-level simulation, Test coverage analysis, Yield learning, IEEE1500, JTAG 1149.x, Memory BIST, Mentor testkompress, Synopsys Tetramax/DFTMAX, VCS simulation, Perl/Shell scripting, Verilog RTL design
Preferred skills
Senior silicon design collaboration, Problem-solving, Detail-oriented approach
Technologies
IEEE1500, JTAG 1149.x, Mentor testkompress, Synopsys Tetramax/DFTMAX, VCS, Perl, Shell, Verilog
Responsibilities
Implement and verify DFT architecture and features, Perform scan insertion and ATPG pattern generation, Verify ATPG patterns with gate-level simulation, Analyze test coverage and test cost reduction, Provide post-silicon support for bring-up and yield enhancement
Seniority
Senior, hands-on IC
