DFT Timing Lead
Core
Ensuring the quality of next generation AMD SoCs through structural DFT, Automatic Test Pattern Generation (ATPG), and Memory Built-In Self-Test (MBIST) techniques.
Role type
Senior IC DFT Silicon Design Engineer
Builds
Next generation AMD System on Chips (SoCs)
Domain
Semiconductor / Digital IC Design
Required skills
DFT architecture, Static Timing Analysis (STA), Timing closure, DFT constraints handling, RTL quality check tools (Spyglass, CDC, Lint), Scripting, Debugging
Preferred skills
DFT synthesis, ATPG, MBIST, Block and Top-level test mode STA, Automation script development
Technologies
Spyglass, CDC, Lint, DFT Synthesis tools, STA tools
Responsibilities
Develop full chip DFT Synthesis and DFT STA constraints; Develop STA constraints for DFT modes (ScanShift, Atspeed, MBIST); Set up DFT timing constraints defining SOC Test STA methodology; Clean up DFT related constraint issues with Design team; Generate and validate timing constraints with Physical Design team; Develop and maintain automation scripts
Seniority
Senior, hands-on IC
