Staff Silicon Design Verification Engineer
Core
Drive verification of complex packet-processing, control-plane, and system-level features for next-generation network processors and SmartNIC technologies.
Role type
Staff Silicon Design Verification Engineer
Builds
High-quality silicon for networking processors and SmartNICs
Domain
Networking silicon, ASIC verification, AI-driven engineering
Deliverable
production ML models
Required skills
UVM, SystemVerilog, Verilog, C, C++, Python, constrained-random testing, simulation/emulation, coverage analysis, automation scripting
Preferred skills
IP-level ASIC verification, data analytics, AI/ML-assisted tools, SystemC, TLM, networking architectures, leadership/mentorship
Technologies
UVM, SystemVerilog, Verilog, C, C++, Python, Perl, Shell, Makefiles, simulation tools, emulation platforms
Responsibilities
Collaborate with architects and engineers to define verification requirements; Build comprehensive verification plans; Develop directed and constrained-random tests and automation infrastructure; Debug test failures and resolve design defects; Drive functional and code coverage closure; Contribute to advanced verification methodologies; Develop automation solutions leveraging AI-assisted workflows.
Seniority
Staff, hands-on IC with mentorship
