Design Verification Engineer - technical lead, Annapurna Labs
Core
Architect and implement end-to-end verification strategies for high-speed I/O and scale-up/out components across the SoC, ensuring thorough coverage of hardware-software interfaces and cross-module functionality for AWS Inferentia and Trainium systems.
Role type
Technical lead Design Verification Engineer (SoC level)
Builds
Custom machine learning data center accelerators (Inferentia, Trainium)
Domain
Cloud computing, Custom Silicon, Hardware verification
Deliverable
production ML models
Required skills
Constrained-random simulation (UVM), Testbench development, Formal verification, Emulation, Test-generation tools, AMBA protocols (AHB/APB/AXI), Interconnect protocols (PCIe, CXL, UCIe), C/C++ programming, Python/Perl scripting
Preferred skills
Experience verifying at multiple levels of logic (IP blocks to SoCs), Object-oriented design, Embedded development
Technologies
UVM, Formal verification tools, Emulation platforms, Test-generation tools, PCIe, CXL, UCIe, AMBA
Responsibilities
Architect and implement end-to-end verification strategies, Drive unified verification plans across multiple environments, Provide technical leadership for verification efforts, Own the technical direction and drive resolution of complex verification challenges, Guide and mentor team members on best practices
Seniority
Senior, hands-on IC with technical leadership
