Full Chip Timing Lead
Core
Lead SoC Full Chip Static Timing Analysis (STA) closure and optimization for high-frequency CPUs, HBM, DDR, and Serdes interfaces.
Role type
Senior IC physical design engineer (timing closure)
Builds
Next-generation processors and AI chips
Domain
Semiconductor / Physical Design
Required skills
Static Timing Analysis (STA), SDC coding, Scripting (TCL, Perl, Python, Makefile), PnR timing convergence, Multi-voltage closure, Hierarchical STA, Timing ECO flow, Yield analysis, Low power physical design flows, Synopsys/Cadence/Mentor tools
Preferred skills
ML techniques in physical design, AMD TileBuilder, 5nm/3nm/2nm tech nodes, Hyperscale experience
Technologies
Synopsys, Cadence, Mentor, TCL, Perl, Python, Makefile, MSCTS, Mesh
Responsibilities
Own full chip timing closure, guide clock build using MSCTS/Mesh, provide design repeater feedback, drive timing improvement initiatives, analyze data and feedback for PD execution, collaborate with PnR engineers for convergence, drive common STA methodology, automate signoff requirements and dashboarding, identify best practices to improve design flow competitiveness
Seniority
Senior, hands-on IC
