ASIC Front-End Methodology Engineer
Core
Own and drive front-end methodology alignment, tool governance, and flow consistency across ASIC front-end implementation flows for multiple chiplets, subsystems, and SoCs.
Role type
Senior IC ASIC front-end methodology engineer (flow governance)
Builds
ASIC front-end implementation flows, tool deployments, and methodology standards for chiplets and SoCs
Domain
Semiconductor / ASIC Design
Required skills
ASIC front-end implementation methodologies, EDA tool flows, tool qualification and version management, RTL-to-GDS flow knowledge, cross-functional coordination, root-cause analysis, automation/scripting, configuration management, signoff requirements
Preferred skills
Leadership and collaboration, AI/ML-driven productivity solutions, customer-facing communication, geographically distributed team management
Technologies
EDA tools, synthesis, constraints, CDC, lint, DFT, STA, physical design, configuration management systems, regression infrastructure
Responsibilities
Drive front-end methodology alignment across chiplets and SoC programs; Manage tool qualification, deployment, and migration; Develop and govern flow infrastructure and design rulesets; Partner with CAD teams on new methodologies and automation; Coordinate with Design, Physical Design, DFT, and Verification teams; Identify and resolve flow gaps and risks; Define and track compliance metrics; Lead technical reviews and mentor engineers
Seniority
Senior, hands-on IC with leadership responsibilities
