Physical Design Lead with STA
Core
Lead Physical Design (PnR) execution and closure for a SubSystem of 10 partitions within a SoC, including high-frequency CPU, HBM, DDR, and Serdes interfaces.
Role type
Senior IC Physical Design Lead
Builds
Next-generation System-on-Chip (SoC) processors
Domain
Semiconductor / Hardware Design
Required skills
Physical Design (PnR), Static Timing Analysis (STA), Synthesis, Place & Route, Power Grid Design, SDC coding, Scripting (TCL, Perl, Python, Makefile), Low Power Design, Physical Verification
Preferred skills
Machine Learning techniques in physical design, AMD TileBuilder, lower tech nodes (5nm/3nm/2nm), Vendor tools (Synopsys, Cadence, Mentor)
Technologies
Synopsys, Cadence, Mentor, TCL, Perl, Python, Makefile
Responsibilities
Own SubSystem PnR execution and closure, Drive closure improvements and convergence from Synthesis to Route, Perform closure signoff on STA, EMIR, and PV, Collaborate with methodology and CAD teams, Automate design signoff requirements and dashboarding, Identify best practices to update flow settings
Seniority
Senior, hands-on IC
