Design Verification Engineer
Core
Architect, develop, and maintain block- and subsystem-level IP verification testbenches, test methodology, and infrastructure for custom hardware accelerators (encryption, authentication, compression, GPU/CPU offloads) powering servers, datacenters, and embedded markets.
Role type
Senior Silicon Design Verification Engineer (ASIC)
Builds
Custom hardware offload engines and verification environments for AMD processors
Domain
Semiconductor / Hardware Design Verification
Deliverable
production ML models
Required skills
Advanced ASIC Functional Verification, System Verilog, UVM, Formal Verification, AI-assisted verification flows, Python/Perl/Ruby scripting, Linux/Windows environments, Debugging complex simulations, Coverage analysis, Test plan architecture
Preferred skills
AI/ML for verification (LLM-generated sequences, automated root-cause analysis), Tapeout experience, Mentoring junior engineers, Power and performance verification (PPV), Emulation support
Technologies
UVM, Formal Verification Tools, AI/ML verification tools, Python, Perl, Ruby, Makefiles, Linux, Windows
Responsibilities
Architect and maintain verification testbenches and infrastructure; Own detailed test plans for new features; Lead regression triage and debug complex simulations; Deploy and evolve verification methodologies (UVM, formal, AI-assisted); Mentor engineers on verification best practices; Reproduce silicon bugs in simulation/formal tools; Conduct code reviews and establish verification standards
Seniority
Senior, hands-on IC with mentorship responsibilities
