ASIC Design Verification Engineer
Core
Own verification strategy and coverage closure for mixed-signal power management IP, driving system-level verification of full SoC while contributing block-level verification and RTL design.
Role type
Senior ASIC Design Verification Engineer (Mixed-Signal)
Builds
Mixed-signal power management ICs and full System-on-Chip (SoC) designs
Domain
Semiconductor / ASIC Design / Mixed-Signal Verification
Required skills
SystemVerilog, UVM, Mixed-signal verification, Real-number modeling (RNM), RTL design, Coverage closure, Regression automation, Debugging, Firmware/RTL co-simulation
Preferred skills
Formal verification, Assertion-based verification (SVA), Emulation/FPGA prototyping, Post-silicon bring-up, Mentorship
Technologies
SystemVerilog, UVM, Verilog-AMS, RNM, Simulation tools, Coverage tools
Responsibilities
Define functional and code coverage goals and drive closure; Develop system-level testbenches for boot, reset, and power state transitions; Verify digital/analog interfaces using real-number models; Partner with analog and RTL design teams on model fidelity; Contribute to RTL design and support post-silicon bring-up.
Seniority
Senior, hands-on IC
