Senior SoC Formal verification Engineer
Core
Develop and execute formal verification strategies for complex IPs, subsystems, and SoC designs using state-of-the-art methodologies.
Role type
Senior IC formal verification engineer
Builds
First-time-right silicon for next-generation computing
Domain
Semiconductor / SoC Design
Required skills
Formal verification methodologies, SystemVerilog Assertions (SVA), Verilog, SystemVerilog, Temporal logic, RTL analysis, Protocol verification, Equivalence checking, Debugging
Preferred skills
JasperGold, VC Formal, Questa Formal, Arm architecture, AMBA protocols, CDC/RDC, Low-power verification, Security verification, Python scripting, Tcl scripting, Perl scripting, Shell scripting, AI-assisted verification
Technologies
SystemVerilog, Verilog, SVA, JasperGold, VC Formal, Questa Formal, Python, Tcl, Perl, Shell
Responsibilities
Develop formal verification strategies for IP, subsystems, and SoCs; Develop SystemVerilog Assertions and formal properties; Apply property checking, protocol verification, and equivalence checking; Own verification deliverables from planning through closure; Architect and maintain reusable verification environments and automation; Develop verification plans and coverage closure strategies; Debug RTL and system-level issues; Collaborate with architecture, design, and validation teams.
Seniority
Senior, hands-on IC