ASIC Engineer
Core
Design and implement digital and/or mixed-signal ASIC blocks from specification through tapeout for RF and mixed-signal chip architectures.
Role type
ASIC Engineer (Digital/Mixed-Signal)
Builds
Mixed-signal and digital integrated circuits interfacing with RF technologies for system-on-chip platforms
Domain
Semiconductor / RF / Wireless Communications
Required skills
RTL design (Verilog/SystemVerilog), Analog/Mixed-signal IC design, Digital design fundamentals (timing, clocking, power), ASIC tool flows (Synopsys, Cadence), UVM verification
Preferred skills
Clock-domain crossing, timing optimization, low-power design, HDL simulators/linting, FPGA development, Python/Tcl scripting
Technologies
FPGA, Python, SystemVerilog, Verilog, Hardware
Responsibilities
Develop RTL and transistor-level designs, integrate digital logic into RF architectures, perform synthesis/timing closure/power optimization, define testbenches, support functional verification and debug, assist with physical implementation, contribute to silicon bring-up and post-silicon validation, document design architecture
Seniority
Mid-level (1–3 years experience)
