Physical Design Engineer
Core
Own the end-to-end library delivery pipeline for standard cell and memory library generation, ensuring quality and consistency across PVT corners.
Role type
Senior IC physical design library engineer
Builds
Standard cell and memory libraries, timing models, and AI-powered dashboards for flow visibility
Domain
Semiconductor VLSI backend / Physical Design
Required skills
Physical Design flow ownership, Library generation (LibBuilder), Memory compiler outputs, PVT corner management, Debugging library failures, Cross-team coordination, EDA tool scripting, AI-assisted automation
Preferred skills
Knowledge of timing concepts, File formats (LEF, DEF, OASIS, Liberty), AI tool usage (Genie, Copilot)
Technologies
LibBuilder, MemView, NDM, Liberty (.lib), LEF, DEF, OASIS, Genie, Claude Code, Copilot
Responsibilities
Execute LibBuilder flow for standard cell and memory library generation, Drive MemView generation across multiple PVT corners, Maintain library quality and consistency, Track and manage PVT corner coverage, Serve as primary point of contact for library-related issues, Perform basic to intermediate debug of library generation failures, Develop and maintain AI-generated dashboards for library health and flow status
Seniority
Senior, hands-on IC
