SoC DFX Scan / ATPG Engineer
Core
Implement, verify, optimize, and deploy advanced Design-for-Test (DFT) solutions including scan insertion and ATPG for next-generation System-on-Chip (SoC) products.
Role type
SoC DFX Scan / ATPG Engineer
Builds
High-quality test architectures and methodologies for complex SoCs (CPU, GPU, AI accelerators)
Domain
Semiconductor / ASIC Design / Digital Logic
Required skills
DFT fundamentals, scan insertion, ATPG execution, scan architecture optimization, test compression, hierarchical test integration, stuck-at/transition/at-speed pattern generation, Verilog/SystemVerilog, digital design flows, scripting (Python/Perl/Tcl/Shell), silicon bring-up support, MBIST/LBIST, JTAG/IJTAG, SSN
Preferred skills
Debugging gate-level simulation and emulation, SoC-level ATPG retargeting, yield analysis, failure analysis, large-scale ASIC development experience
Technologies
Python, Perl, Tcl, Shell, Verilog, SystemVerilog, MBIST, LBIST, JTAG, IJTAG, SSN, PLL-based testing
Responsibilities
Drive end-to-end SoC-level scan insertion and ATPG execution; Develop and optimize scan chains and test compression strategies; Analyze scan coverage and ATPG results; Support ATPG retargeting and hierarchical test integration; Debug scan, simulation, and emulation issues from block to full-chip; Develop automation and scripting solutions for DFT productivity
Seniority
Mid-Senior level IC Engineer
