Senior Signal and Power Integrity Engineer - Hardware
Core
Crafting creative Signal Integrity (SI) and Power Integrity (PI) solutions for complex high-speed system design problems, including system-level simulations, 3D EM modeling, and Power Delivery Network (PDN) optimization.
Role type
Senior IC Signal and Power Integrity Engineer
Builds
High-speed interface solutions (NVlinks, USB-4, PCIe5, GDDR6, LP5X) for NVIDIA GPUs and AI systems
Domain
Semiconductor hardware, high-speed digital interfaces, electromagnetic compatibility
Required skills
System-level signal integrity simulation, 3D EM modeling (ANSYS HFSS/Q3D/SIWAVE), Power Delivery Network (PDN) design and optimization, PDN evaluation using layout extraction and SPICE-based time domain simulations, system-level timing or loss budget analysis, high-speed interface standards knowledge (PCIe, USB, SATA, HDMI, HBM, DDR5, GDDR6, LPDDR5X)
Preferred skills
Lab measurements and debugging (oscilloscope, spectrum analyzer, VNA, TDR, DSO), SI lab correlation, circuit design, board/pkg component design, link architecture, timing budget methodologies, JMP/MATLAB for simulation automation and data analysis
Technologies
ANSYS HFSS, ANSYS Q3D, ANSYS SIWAVE, JMP, MATLAB, VNA, TDR, DSO, ParBERT
Responsibilities
Perform system-level signal integrity simulations for high-speed interfaces; Model vias, connectors, sockets, and system components in 3D EM tools; Design and optimize Power Delivery Networks (PDN) across packages and PCBs; Improve SI/PI models through lab measurements; Automate simulation, gather data, and perform analysis/visualization
Seniority
Senior, hands-on IC
