Senior Circuit Timing Engineer
Core
Senior IC engineer driving timing analysis, signoff, and transistor-level design for custom digital and mixed-signal macros in deep submicron technologies.
Role type
Senior IC circuit timing engineer (digital/AMS)
Builds
Custom circuit macros, silicon designs, and hardware security/power management solutions for NVIDIA processors
Domain
Semiconductor hardware design, deep submicron digital and analog mixed-signal (AMS)
Required skills
Static timing analysis (STA), transistor-level circuit design, SPICE simulation, timing constraints management, ECO implementation, process variation modeling, EM/IR analysis
Preferred skills
Low power circuit design (power gating, multi-Vt), post-silicon characterization, full silicon design flow ownership, timing closure for AMS designs
Technologies
Nanotime, PrimeTime, Tempus, SPICE, STA tools, .libs
Responsibilities
Drive timing analysis and signoff of custom circuit macros; Validate timing using STA tools and SPICE simulations; Develop timing models and methodology for custom macro designs; Collaborate on power, performance, area, and reliability optimization; Integrate AI/ML techniques into design methodology; Work with PD, DFX, and Clocks teams on timing convergence and DFT
Seniority
Senior, hands-on IC
