ASIC Physical Design Engineer
Core
ASIC Physical Design Engineer responsible for RTL-to-GDSII flow, including synthesis, timing analysis/closure, formal verification, and floorplanning for the world's biggest chip.
Role type
Senior IC physical design engineer
Builds
Advanced ASIC chips
Domain
Semiconductor / IC Design
Required skills
RTL-to-GDSII flow, STA, timing closure, synthesis, formal verification, floorplanning, constraint creation, Python/Perl/TCL scripting
Preferred skills
Advanced Python/Perl/TCL scripting, English communication
Technologies
Synopsys (FC/DC/PT/Formality), Cadence (RC Compiler/Genus/LEC)
Responsibilities
Perform STA for hierarchical design, create and validate constraints, achieve timing closure at partition and full chip levels, implement chip partition and floorplan, develop and enhance timing closure flow from frontend to backend, automate flows and methodologies
Seniority
Junior to Senior, hands-on IC
