Memory Silicon Validation Engineer
Core
Senior engineer owning high-speed memory bring-up, characterization, and qualification for flagship GPU, CPU, and SoC programs, focusing on root-cause analysis of memory marginality and building AI-accelerated qualification capabilities.
Role type
Senior IC memory silicon validation engineer
Builds
High-speed memory interfaces (GDDR, LPDDR, HBM) for GPUs, CPUs, and SoCs
Domain
Semiconductor / High-performance computing / Memory subsystems
Deliverable
production ML models
Required skills
High-speed memory interface bring-up (GDDR, LPDDR, HBM), root-cause analysis of memory failures, timing margin analysis, IO tuning, multi-vendor DRAM qualification, AI-driven workflow design for margin data analysis, oscilloscope and protocol analyzer usage, PCB stack-up and board layout knowledge
Preferred skills
Experience codifying reusable qualification methodology and debug playbooks, agentic workflows or RAG-grounded debug assistants, automated shmoo analysis, ML-driven margin prediction
Technologies
GDDR, LPDDR, HBM, shmoo analysis, AI/ML tools for margin prediction
Responsibilities
Bring up high-speed memory interfaces from first power-on through full PVT characterization, lead root-cause closure on multi-team memory failures spanning silicon to workload, design and deploy AI-enabled workflows for margin data analysis and failure signature detection, partner with pre-Si architecture and DV teams to translate features into validation plans, work across globally distributed teams including silicon design and DRAM vendors
