Physical Design STA CAD Engineer
Core
Developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.
Role type
Senior IC physical design STA CAD engineer
Builds
Networking chips and SOCs
Domain
Semiconductor / Networking Silicon
Required skills
Physical Design, Backend CAD, Static Timing Analysis (STA), Timing closure methodologies, Power Integrity, Power Estimation, IR-drop, Electromigration (EM) analysis, Back-end verification
Preferred skills
Signoff domains (STA, Power Estimation, Power Integrity, Formal equivalence), Tcl/Perl/Python scripting
Technologies
PrimeTime, PrimePower, RedHawk, Formality
Responsibilities
Develop physical design, STA, Logic eq, and Power Integrity flows; Collaborate with block owners and full Chip STA engineers for convergence; Create unique solutions for state-of-the-art physical design problems; Participate in developing flow and tool methodologies for timing, power, and noise analysis.
Seniority
Mid-level, hands-on IC
