ASIC Design and STA Engineer
Core
Full chip and/or chiplet level Static Timing Analysis (STA) convergence from early stages to signoff for high-speed communication devices and AI platforms.
Role type
Senior IC ASIC STA Engineer
Builds
High-speed communication devices and AI platform chips
Domain
Semiconductor / ASIC Physical Design
Required skills
STA convergence, clock planning, RTL2GDS flow, timing optimization, constraint definition, EDA tool usage
Preferred skills
None stated
Technologies
Synopsys Primetime, Synopsys, Cadence
Responsibilities
Full chip and/or chiplet level STA convergence from early stages to signoff, top level floor plan and clock planning, optimize CAD signoff flows and methodologies, integrate timing for digital partitions and analog IPs, define and implement constraints for various work modes with logic design and DFT engineers
Seniority
Mid-level, hands-on IC
