Senior ASIC Physical Design Engineer, Netlisting
Core
Drive physical design of high-frequency, low-power CPUs, GPUs, and SoCs at block, cluster, and full-chip levels, focusing on netlist quality, equivalence checking, timing closure, and asynchronous verification.
Role type
Senior ASIC Physical Design Engineer (Netlisting)
Builds
High-performance CPUs, GPUs, and System-on-Chips (SoCs)
Domain
Semiconductor / ASIC Design
Deliverable
production ML models
Required skills
Logic equivalence checking (FV), Static Timing Analysis (STA), Clock-domain-crossing (CDC) checking, MTBF analysis, Logic synthesis, Timing constraints management, EDA tools, Scripting (Perl, TCL, Python)
Preferred skills
DFT timing closure, AI utilization for workflow improvement
Technologies
Industry-standard EDA tools, Perl, TCL, Make, Python
Responsibilities
Drive physical design for CPUs, GPUs, and SoCs; Perform equivalence checking and asynchronous verification; Manage timing convergence and ECO generation; Generate and manage timing constraints.
Seniority
Senior, hands-on IC
