Senior ASIC Design Engineer - DFX
Core
Design-for-Test (DFT) architecture, design, implementation, and verification for next-generation System-on-Chip (SoC) products, covering the full silicon lifecycle from pre-silicon to post-silicon.
Role type
Senior ASIC Design Engineer (DFT)
Builds
DFT IPs (e.g., fuse controllers), test methodologies, and verification plans for complex semiconductor chips.
Domain
Semiconductor / ASIC Design / DFT
Required skills
SoC architecture, RTL design, DFT design and methodology, post-silicon bring-up, scripting (Python/Perl/Tcl), micro-architecture
Preferred skills
UVM-based verification, fuse/eFuse/security block design, cross-functional collaboration
Technologies
Verilog, UVM, Python, Perl, Tcl, ATE
Responsibilities
Own architecture and design of fuse controller and other DFT IPs; Develop and enhance DFT methodologies; Define feature sets with architects and platform teams; Partner with design, verification, synthesis, and timing teams; Create and execute test plans for full-chip verification; Support post-silicon bring-up, debug, and validation; Mentor junior engineers on test design strategies.
Seniority
Senior, hands-on IC
