Senior Digital Design Engineer
Core
Designing high-performance, area, and power-efficient RTL blocks for NVLink Fusion-based AI infrastructure System-on-Chips.
Role type
Senior Digital Design Engineer (ASIC/Semiconductor)
Builds
NVLink Fusion System-on-Chips for rack-scale AI connectivity
Domain
Semiconductor / AI Infrastructure
Deliverable
production ML models
Required skills
RTL design, micro-architecture specification, ASIC design flows, high-speed connectivity protocols (NVLink, PCI-Express, Ethernet, UCIE), high bandwidth datapath blocks, IP selection and integration
Preferred skills
None stated
Technologies
NVLink, PCI-Express, Ethernet, UCIE, RTL, ASIC
Responsibilities
Analyze architectural requirements and perform trade-off analysis for RTL blocks; Craft micro-architecture specifications and implement verified, synthesis and timing clean blocks; Collaborate with chip architects, verification engineers, and SoC integration engineers; Identify and integrate IP solutions for specific use cases
Seniority
Senior, hands-on IC
