Senior Memory Mask Design Engineer
Core
Lead architecture and layout design of high-performance, high-speed CMOS memory subsystems (control logic, sense amplifiers, I/O blocks, bit-cell arrays, decoders) in advanced technology nodes (3nm, 5nm, 7nm).
Role type
Senior IC memory mask design engineer
Builds
High-performance memory chips for NVIDIA GPUs
Domain
Semiconductor / Advanced CMOS Process
Required skills
IC layout in advanced CMOS nodes, memory subsystem architecture, physical verification (DRC, LVS, density analysis), IR drop and EM mitigation, memory compilers, floor planning, block level routing, layout dependent effects (LOD, Dummification, fills)
Preferred skills
Mentorship of junior engineers, resource management, cross-functional teamwork
Technologies
Cadence EDA tools
Responsibilities
Implement IC layout of innovative high-speed CMOS integrated circuits; Lead architecture and layout design of key memory subsystems; Direct custom layout and verification of complex memory cells; Optimize physical verification activities; Drive resolution of complex physical design issues; Provide guidance on IR drop and EM mitigation strategies; Develop memory compilers
Seniority
Senior, hands-on IC
